STM32LIB
stm32f0xx_tim.h
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1 
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F0XX_TIM_H
38 #define __STM32F0XX_TIM_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f0xx.h"
46 
55 /* Exported types ------------------------------------------------------------*/
56 
62 typedef struct
63 {
64  uint16_t TIM_Prescaler;
67  uint16_t TIM_CounterMode;
70  uint32_t TIM_Period;
74  uint16_t TIM_ClockDivision;
77  uint8_t TIM_RepetitionCounter;
85 } TIM_TimeBaseInitTypeDef;
86 
91 typedef struct
92 {
93  uint16_t TIM_OCMode;
96  uint16_t TIM_OutputState;
99  uint16_t TIM_OutputNState;
103  uint32_t TIM_Pulse;
107  uint16_t TIM_OCPolarity;
110  uint16_t TIM_OCNPolarity;
114  uint16_t TIM_OCIdleState;
118  uint16_t TIM_OCNIdleState;
121 } TIM_OCInitTypeDef;
122 
127 typedef struct
128 {
129 
130  uint16_t TIM_Channel;
133  uint16_t TIM_ICPolarity;
136  uint16_t TIM_ICSelection;
139  uint16_t TIM_ICPrescaler;
142  uint16_t TIM_ICFilter;
144 } TIM_ICInitTypeDef;
145 
151 typedef struct
152 {
153 
154  uint16_t TIM_OSSRState;
157  uint16_t TIM_OSSIState;
160  uint16_t TIM_LOCKLevel;
163  uint16_t TIM_DeadTime;
167  uint16_t TIM_Break;
170  uint16_t TIM_BreakPolarity;
173  uint16_t TIM_AutomaticOutput;
175 } TIM_BDTRInitTypeDef;
176 
181 /* Exported constants --------------------------------------------------------*/
182 
183 
188 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
189  ((PERIPH) == TIM2) || \
190  ((PERIPH) == TIM3) || \
191  ((PERIPH) == TIM6) || \
192  ((PERIPH) == TIM7) || \
193  ((PERIPH) == TIM14)|| \
194  ((PERIPH) == TIM15)|| \
195  ((PERIPH) == TIM16)|| \
196  ((PERIPH) == TIM17))
197 
198 /* LIST1: TIM 1 */
199 #define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
200 
201 /* LIST2: TIM 1, 15, 16 and 17 */
202 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
203  ((PERIPH) == TIM15)|| \
204  ((PERIPH) == TIM16)|| \
205  ((PERIPH) == TIM17))
206 
207 /* LIST3: TIM 1, 2 and 3 */
208 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
209  ((PERIPH) == TIM2) || \
210  ((PERIPH) == TIM3))
211 
212 /* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
213 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
214  ((PERIPH) == TIM2) || \
215  ((PERIPH) == TIM3) || \
216  ((PERIPH) == TIM14) || \
217  ((PERIPH) == TIM15)|| \
218  ((PERIPH) == TIM16)|| \
219  ((PERIPH) == TIM17))
220 
221 /* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
222 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
223  ((PERIPH) == TIM2) || \
224  ((PERIPH) == TIM3) || \
225  ((PERIPH) == TIM15)|| \
226  ((PERIPH) == TIM16)|| \
227  ((PERIPH) == TIM17))
228 
229 /* LIST6: TIM 1, 2, 3 and 15 */
230 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
231  ((PERIPH) == TIM2) || \
232  ((PERIPH) == TIM3) || \
233  ((PERIPH) == TIM15))
234 
235 /* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
236 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
237  ((PERIPH) == TIM2) || \
238  ((PERIPH) == TIM3) || \
239  ((PERIPH) == TIM6) || \
240  ((PERIPH) == TIM7) || \
241  ((PERIPH) == TIM14))
242 
243 /* LIST8: TIM 1, 2, 3 and 14 */
244 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
245  ((PERIPH) == TIM2) || \
246  ((PERIPH) == TIM3) || \
247  ((PERIPH) == TIM14))
248 
249 /* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
250 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
251  ((PERIPH) == TIM2) || \
252  ((PERIPH) == TIM3) || \
253  ((PERIPH) == TIM6) || \
254  ((PERIPH) == TIM7) || \
255  ((PERIPH) == TIM15))
256 
257 /* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
258 #define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
259  ((PERIPH) == TIM2) || \
260  ((PERIPH) == TIM3) || \
261  ((PERIPH) == TIM6) || \
262  ((PERIPH) == TIM7) || \
263  ((PERIPH) == TIM15)|| \
264  ((PERIPH) == TIM16)|| \
265  ((PERIPH) == TIM17))
266 
267 /* LIST1: TIM 11 */
268 #define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)
269 
270 
279 #define TIM_OCMode_Timing ((uint16_t)0x0000)
280 #define TIM_OCMode_Active ((uint16_t)0x0010)
281 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
282 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
283 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
284 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
285 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
286  ((MODE) == TIM_OCMode_Active) || \
287  ((MODE) == TIM_OCMode_Inactive) || \
288  ((MODE) == TIM_OCMode_Toggle)|| \
289  ((MODE) == TIM_OCMode_PWM1) || \
290  ((MODE) == TIM_OCMode_PWM2))
291 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
292  ((MODE) == TIM_OCMode_Active) || \
293  ((MODE) == TIM_OCMode_Inactive) || \
294  ((MODE) == TIM_OCMode_Toggle)|| \
295  ((MODE) == TIM_OCMode_PWM1) || \
296  ((MODE) == TIM_OCMode_PWM2) || \
297  ((MODE) == TIM_ForcedAction_Active) || \
298  ((MODE) == TIM_ForcedAction_InActive))
299 
307 #define TIM_OPMode_Single ((uint16_t)0x0008)
308 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
309 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
310  ((MODE) == TIM_OPMode_Repetitive))
311 
319 #define TIM_Channel_1 ((uint16_t)0x0000)
320 #define TIM_Channel_2 ((uint16_t)0x0004)
321 #define TIM_Channel_3 ((uint16_t)0x0008)
322 #define TIM_Channel_4 ((uint16_t)0x000C)
323 
324 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
325  ((CHANNEL) == TIM_Channel_2) || \
326  ((CHANNEL) == TIM_Channel_3) || \
327  ((CHANNEL) == TIM_Channel_4))
328 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
329  ((CHANNEL) == TIM_Channel_2) || \
330  ((CHANNEL) == TIM_Channel_3))
331 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
332  ((CHANNEL) == TIM_Channel_2))
333 
342 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
343 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
344 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
345 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
346  ((DIV) == TIM_CKD_DIV2) || \
347  ((DIV) == TIM_CKD_DIV4))
348 
356 #define TIM_CounterMode_Up ((uint16_t)0x0000)
357 #define TIM_CounterMode_Down ((uint16_t)0x0010)
358 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
359 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
360 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
361 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
362  ((MODE) == TIM_CounterMode_Down) || \
363  ((MODE) == TIM_CounterMode_CenterAligned1) || \
364  ((MODE) == TIM_CounterMode_CenterAligned2) || \
365  ((MODE) == TIM_CounterMode_CenterAligned3))
366 
374 #define TIM_OCPolarity_High ((uint16_t)0x0000)
375 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
376 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
377  ((POLARITY) == TIM_OCPolarity_Low))
378 
386 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
387 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
388 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
389  ((POLARITY) == TIM_OCNPolarity_Low))
390 
398 #define TIM_OutputState_Disable ((uint16_t)0x0000)
399 #define TIM_OutputState_Enable ((uint16_t)0x0001)
400 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
401  ((STATE) == TIM_OutputState_Enable))
402 
410 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
411 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
412 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
413  ((STATE) == TIM_OutputNState_Enable))
414 
422 #define TIM_CCx_Enable ((uint16_t)0x0001)
423 #define TIM_CCx_Disable ((uint16_t)0x0000)
424 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
425  ((CCX) == TIM_CCx_Disable))
426 
434 #define TIM_CCxN_Enable ((uint16_t)0x0004)
435 #define TIM_CCxN_Disable ((uint16_t)0x0000)
436 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
437  ((CCXN) == TIM_CCxN_Disable))
438 
446 #define TIM_Break_Enable ((uint16_t)0x1000)
447 #define TIM_Break_Disable ((uint16_t)0x0000)
448 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
449  ((STATE) == TIM_Break_Disable))
450 
458 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
459 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
460 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
461  ((POLARITY) == TIM_BreakPolarity_High))
462 
470 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
471 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
472 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
473  ((STATE) == TIM_AutomaticOutput_Disable))
474 
482 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
483 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
484 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
485 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
486 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
487  ((LEVEL) == TIM_LOCKLevel_1) || \
488  ((LEVEL) == TIM_LOCKLevel_2) || \
489  ((LEVEL) == TIM_LOCKLevel_3))
490 
498 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
499 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
500 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
501  ((STATE) == TIM_OSSIState_Disable))
502 
510 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
511 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
512 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
513  ((STATE) == TIM_OSSRState_Disable))
514 
522 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
523 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
524 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
525  ((STATE) == TIM_OCIdleState_Reset))
526 
534 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
535 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
536 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
537  ((STATE) == TIM_OCNIdleState_Reset))
538 
546 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
547 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
548 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
549 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
550  ((POLARITY) == TIM_ICPolarity_Falling)|| \
551  ((POLARITY) == TIM_ICPolarity_BothEdge))
552 
560 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
562 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
564 #define TIM_ICSelection_TRC ((uint16_t)0x0003)
565 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
566  ((SELECTION) == TIM_ICSelection_IndirectTI) || \
567  ((SELECTION) == TIM_ICSelection_TRC))
568 
576 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
577 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
578 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
579 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
580 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
581  ((PRESCALER) == TIM_ICPSC_DIV2) || \
582  ((PRESCALER) == TIM_ICPSC_DIV4) || \
583  ((PRESCALER) == TIM_ICPSC_DIV8))
584 
592 #define TIM_IT_Update ((uint16_t)0x0001)
593 #define TIM_IT_CC1 ((uint16_t)0x0002)
594 #define TIM_IT_CC2 ((uint16_t)0x0004)
595 #define TIM_IT_CC3 ((uint16_t)0x0008)
596 #define TIM_IT_CC4 ((uint16_t)0x0010)
597 #define TIM_IT_COM ((uint16_t)0x0020)
598 #define TIM_IT_Trigger ((uint16_t)0x0040)
599 #define TIM_IT_Break ((uint16_t)0x0080)
600 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
601 
602 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
603  ((IT) == TIM_IT_CC1) || \
604  ((IT) == TIM_IT_CC2) || \
605  ((IT) == TIM_IT_CC3) || \
606  ((IT) == TIM_IT_CC4) || \
607  ((IT) == TIM_IT_COM) || \
608  ((IT) == TIM_IT_Trigger) || \
609  ((IT) == TIM_IT_Break))
610 
618 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
619 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
620 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
621 #define TIM_DMABase_DIER ((uint16_t)0x0003)
622 #define TIM_DMABase_SR ((uint16_t)0x0004)
623 #define TIM_DMABase_EGR ((uint16_t)0x0005)
624 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
625 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
626 #define TIM_DMABase_CCER ((uint16_t)0x0008)
627 #define TIM_DMABase_CNT ((uint16_t)0x0009)
628 #define TIM_DMABase_PSC ((uint16_t)0x000A)
629 #define TIM_DMABase_ARR ((uint16_t)0x000B)
630 #define TIM_DMABase_RCR ((uint16_t)0x000C)
631 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
632 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
633 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
634 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
635 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
636 #define TIM_DMABase_DCR ((uint16_t)0x0012)
637 #define TIM_DMABase_OR ((uint16_t)0x0013)
638 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
639  ((BASE) == TIM_DMABase_CR2) || \
640  ((BASE) == TIM_DMABase_SMCR) || \
641  ((BASE) == TIM_DMABase_DIER) || \
642  ((BASE) == TIM_DMABase_SR) || \
643  ((BASE) == TIM_DMABase_EGR) || \
644  ((BASE) == TIM_DMABase_CCMR1) || \
645  ((BASE) == TIM_DMABase_CCMR2) || \
646  ((BASE) == TIM_DMABase_CCER) || \
647  ((BASE) == TIM_DMABase_CNT) || \
648  ((BASE) == TIM_DMABase_PSC) || \
649  ((BASE) == TIM_DMABase_ARR) || \
650  ((BASE) == TIM_DMABase_RCR) || \
651  ((BASE) == TIM_DMABase_CCR1) || \
652  ((BASE) == TIM_DMABase_CCR2) || \
653  ((BASE) == TIM_DMABase_CCR3) || \
654  ((BASE) == TIM_DMABase_CCR4) || \
655  ((BASE) == TIM_DMABase_BDTR) || \
656  ((BASE) == TIM_DMABase_DCR) || \
657  ((BASE) == TIM_DMABase_OR))
658 
667 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
668 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
669 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
670 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
671 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
672 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
673 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
674 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
675 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
676 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
677 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
678 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
679 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
680 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
681 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
682 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
683 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
684 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
685 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
686  ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
687  ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
688  ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
689  ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
690  ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
691  ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
692  ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
693  ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
694  ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
695  ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
696  ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
697  ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
698  ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
699  ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
700  ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
701  ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
702  ((LENGTH) == TIM_DMABurstLength_18Transfers))
703 
711 #define TIM_DMA_Update ((uint16_t)0x0100)
712 #define TIM_DMA_CC1 ((uint16_t)0x0200)
713 #define TIM_DMA_CC2 ((uint16_t)0x0400)
714 #define TIM_DMA_CC3 ((uint16_t)0x0800)
715 #define TIM_DMA_CC4 ((uint16_t)0x1000)
716 #define TIM_DMA_COM ((uint16_t)0x2000)
717 #define TIM_DMA_Trigger ((uint16_t)0x4000)
718 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
719 
728 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
729 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
730 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
731 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
732 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
733  ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
734  ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
735  ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
736 
744 #define TIM_TS_ITR0 ((uint16_t)0x0000)
745 #define TIM_TS_ITR1 ((uint16_t)0x0010)
746 #define TIM_TS_ITR2 ((uint16_t)0x0020)
747 #define TIM_TS_ITR3 ((uint16_t)0x0030)
748 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
749 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
750 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
751 #define TIM_TS_ETRF ((uint16_t)0x0070)
752 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
753  ((SELECTION) == TIM_TS_ITR1) || \
754  ((SELECTION) == TIM_TS_ITR2) || \
755  ((SELECTION) == TIM_TS_ITR3) || \
756  ((SELECTION) == TIM_TS_TI1F_ED) || \
757  ((SELECTION) == TIM_TS_TI1FP1) || \
758  ((SELECTION) == TIM_TS_TI2FP2) || \
759  ((SELECTION) == TIM_TS_ETRF))
760 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
761  ((SELECTION) == TIM_TS_ITR1) || \
762  ((SELECTION) == TIM_TS_ITR2) || \
763  ((SELECTION) == TIM_TS_ITR3))
764 
772 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
773 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
774 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
775 
783 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
784 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
785 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
786  ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
787 
795 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
796 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
797 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
798  ((RELOAD) == TIM_PSCReloadMode_Immediate))
799 
807 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
808 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
809 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
810  ((ACTION) == TIM_ForcedAction_InActive))
811 
819 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
820 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
821 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
822 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
823  ((MODE) == TIM_EncoderMode_TI2) || \
824  ((MODE) == TIM_EncoderMode_TI12))
825 
834 #define TIM_EventSource_Update ((uint16_t)0x0001)
835 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
836 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
837 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
838 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
839 #define TIM_EventSource_COM ((uint16_t)0x0020)
840 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
841 #define TIM_EventSource_Break ((uint16_t)0x0080)
842 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
843 
852 #define TIM_UpdateSource_Global ((uint16_t)0x0000)
855 #define TIM_UpdateSource_Regular ((uint16_t)0x0001)
856 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
857  ((SOURCE) == TIM_UpdateSource_Regular))
858 
866 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
867 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
868 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
869  ((STATE) == TIM_OCPreload_Disable))
870 
878 #define TIM_OCFast_Enable ((uint16_t)0x0004)
879 #define TIM_OCFast_Disable ((uint16_t)0x0000)
880 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
881  ((STATE) == TIM_OCFast_Disable))
882 
891 #define TIM_OCClear_Enable ((uint16_t)0x0080)
892 #define TIM_OCClear_Disable ((uint16_t)0x0000)
893 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
894  ((STATE) == TIM_OCClear_Disable))
895 
903 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
904 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
905 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
906 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
907 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
908 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
909 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
910 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
911 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
912  ((SOURCE) == TIM_TRGOSource_Enable) || \
913  ((SOURCE) == TIM_TRGOSource_Update) || \
914  ((SOURCE) == TIM_TRGOSource_OC1) || \
915  ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
916  ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
917  ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
918  ((SOURCE) == TIM_TRGOSource_OC4Ref))
919 
927 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
928 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
929 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
930 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
931 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
932  ((MODE) == TIM_SlaveMode_Gated) || \
933  ((MODE) == TIM_SlaveMode_Trigger) || \
934  ((MODE) == TIM_SlaveMode_External1))
935 
943 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
944 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
945 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
946  ((STATE) == TIM_MasterSlaveMode_Disable))
947 
955 #define TIM_FLAG_Update ((uint16_t)0x0001)
956 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
957 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
958 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
959 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
960 #define TIM_FLAG_COM ((uint16_t)0x0020)
961 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
962 #define TIM_FLAG_Break ((uint16_t)0x0080)
963 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
964 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
965 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
966 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
967 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
968  ((FLAG) == TIM_FLAG_CC1) || \
969  ((FLAG) == TIM_FLAG_CC2) || \
970  ((FLAG) == TIM_FLAG_CC3) || \
971  ((FLAG) == TIM_FLAG_CC4) || \
972  ((FLAG) == TIM_FLAG_COM) || \
973  ((FLAG) == TIM_FLAG_Trigger) || \
974  ((FLAG) == TIM_FLAG_Break) || \
975  ((FLAG) == TIM_FLAG_CC1OF) || \
976  ((FLAG) == TIM_FLAG_CC2OF) || \
977  ((FLAG) == TIM_FLAG_CC3OF) || \
978  ((FLAG) == TIM_FLAG_CC4OF))
979 
980 
981 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
982 
991 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
992 
1000 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
1001 
1008 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
1009 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
1010 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
1011  ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
1012 
1019 #define TIM14_GPIO ((uint16_t)0x0000)
1020 #define TIM14_RTC_CLK ((uint16_t)0x0001)
1021 #define TIM14_HSEDiv32 ((uint16_t)0x0002)
1022 #define TIM14_MCO ((uint16_t)0x0003)
1023 
1024 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \
1025  ((TIM_REMAP) == TIM14_RTC_CLK) || \
1026  ((TIM_REMAP) == TIM14_HSEDiv32) || \
1027  ((TIM_REMAP) == TIM14_MCO))
1028 
1036 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
1037 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
1038 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
1039 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
1040 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
1041 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
1042 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
1043 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
1044 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
1045 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1046 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1047 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1048 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1049 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1050 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1051 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1052 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1053 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1054 
1063 #ifdef __cplusplus
1064 }
1065 #endif
1066 
1067 #endif /*__STM32F0XX_TIM_H */
1068 
1077 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
TIM_TimeBaseInitTypeDef::TIM_RepetitionCounter
uint8_t TIM_RepetitionCounter
Definition: stm32f0xx_tim.h:77
TIM_OCInitTypeDef::TIM_OCNPolarity
uint16_t TIM_OCNPolarity
Definition: stm32f0xx_tim.h:110
TIM_OCInitTypeDef::TIM_OCNIdleState
uint16_t TIM_OCNIdleState
Definition: stm32f0xx_tim.h:118
TIM_ICInitTypeDef::TIM_ICFilter
uint16_t TIM_ICFilter
Definition: stm32f0xx_tim.h:142
TIM_BDTRInitTypeDef::TIM_BreakPolarity
uint16_t TIM_BreakPolarity
Definition: stm32f0xx_tim.h:170
TIM_ICInitTypeDef::TIM_ICPolarity
uint16_t TIM_ICPolarity
Definition: stm32f0xx_tim.h:133
TIM_BDTRInitTypeDef::TIM_OSSIState
uint16_t TIM_OSSIState
Definition: stm32f0xx_tim.h:157
TIM_TimeBaseInitTypeDef::TIM_CounterMode
uint16_t TIM_CounterMode
Definition: stm32f0xx_tim.h:67
TIM_BDTRInitTypeDef::TIM_Break
uint16_t TIM_Break
Definition: stm32f0xx_tim.h:167
TIM_ICInitTypeDef::TIM_ICSelection
uint16_t TIM_ICSelection
Definition: stm32f0xx_tim.h:136
TIM_OCInitTypeDef
TIM Output Compare Init structure definition.
Definition: stm32f0xx_tim.h:91
TIM_TimeBaseInitTypeDef
TIM Time Base Init structure definition.
Definition: stm32f0xx_tim.h:62
TIM_OCInitTypeDef::TIM_OCPolarity
uint16_t TIM_OCPolarity
Definition: stm32f0xx_tim.h:107
TIM_TimeBaseInitTypeDef::TIM_ClockDivision
uint16_t TIM_ClockDivision
Definition: stm32f0xx_tim.h:74
TIM_BDTRInitTypeDef::TIM_LOCKLevel
uint16_t TIM_LOCKLevel
Definition: stm32f0xx_tim.h:160
TIM_ICInitTypeDef::TIM_ICPrescaler
uint16_t TIM_ICPrescaler
Definition: stm32f0xx_tim.h:139
TIM_OCInitTypeDef::TIM_Pulse
uint32_t TIM_Pulse
Definition: stm32f0xx_tim.h:103
TIM_BDTRInitTypeDef::TIM_OSSRState
uint16_t TIM_OSSRState
Definition: stm32f0xx_tim.h:154
TIM_BDTRInitTypeDef::TIM_DeadTime
uint16_t TIM_DeadTime
Definition: stm32f0xx_tim.h:163
TIM_ICInitTypeDef::TIM_Channel
uint16_t TIM_Channel
Definition: stm32f0xx_tim.h:130
TIM_OCInitTypeDef::TIM_OutputNState
uint16_t TIM_OutputNState
Definition: stm32f0xx_tim.h:99
TIM_TimeBaseInitTypeDef::TIM_Prescaler
uint16_t TIM_Prescaler
Definition: stm32f0xx_tim.h:64
TIM_OCInitTypeDef::TIM_OCIdleState
uint16_t TIM_OCIdleState
Definition: stm32f0xx_tim.h:114
TIM_ICInitTypeDef
TIM Input Capture Init structure definition.
Definition: stm32f0xx_tim.h:127
TIM_TimeBaseInitTypeDef::TIM_Period
uint32_t TIM_Period
Definition: stm32f0xx_tim.h:70
TIM_BDTRInitTypeDef::TIM_AutomaticOutput
uint16_t TIM_AutomaticOutput
Definition: stm32f0xx_tim.h:173
TIM_OCInitTypeDef::TIM_OutputState
uint16_t TIM_OutputState
Definition: stm32f0xx_tim.h:96
TIM_BDTRInitTypeDef
TIM_BDTR structure definition.
Definition: stm32f0xx_tim.h:151
TIM_OCInitTypeDef::TIM_OCMode
uint16_t TIM_OCMode
Definition: stm32f0xx_tim.h:93
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