TIM_DMA_Base_address

Macros
#define	TIM_DMABase_CR1   ((uint16_t)0x0000)
#define	TIM_DMABase_CR2   ((uint16_t)0x0001)
#define	TIM_DMABase_SMCR   ((uint16_t)0x0002)
#define	TIM_DMABase_DIER   ((uint16_t)0x0003)
#define	TIM_DMABase_SR   ((uint16_t)0x0004)
#define	TIM_DMABase_EGR   ((uint16_t)0x0005)
#define	TIM_DMABase_CCMR1   ((uint16_t)0x0006)
#define	TIM_DMABase_CCMR2   ((uint16_t)0x0007)
#define	TIM_DMABase_CCER   ((uint16_t)0x0008)
#define	TIM_DMABase_CNT   ((uint16_t)0x0009)
#define	TIM_DMABase_PSC   ((uint16_t)0x000A)
#define	TIM_DMABase_ARR   ((uint16_t)0x000B)
#define	TIM_DMABase_RCR   ((uint16_t)0x000C)
#define	TIM_DMABase_CCR1   ((uint16_t)0x000D)
#define	TIM_DMABase_CCR2   ((uint16_t)0x000E)
#define	TIM_DMABase_CCR3   ((uint16_t)0x000F)
#define	TIM_DMABase_CCR4   ((uint16_t)0x0010)
#define	TIM_DMABase_BDTR   ((uint16_t)0x0011)
#define	TIM_DMABase_DCR   ((uint16_t)0x0012)
#define	TIM_DMABase_OR   ((uint16_t)0x0013)
#define	IS_TIM_DMA_BASE(BASE)

Detailed Description

Macro Definition Documentation

#define TIM_DMABase_CR1   ((uint16_t)0x0000)

#define TIM_DMABase_CR2   ((uint16_t)0x0001)

#define TIM_DMABase_SMCR   ((uint16_t)0x0002)

#define TIM_DMABase_DIER   ((uint16_t)0x0003)

#define TIM_DMABase_SR   ((uint16_t)0x0004)

#define TIM_DMABase_EGR   ((uint16_t)0x0005)

#define TIM_DMABase_CCMR1   ((uint16_t)0x0006)

#define TIM_DMABase_CCMR2   ((uint16_t)0x0007)

#define TIM_DMABase_CCER   ((uint16_t)0x0008)

#define TIM_DMABase_CNT   ((uint16_t)0x0009)

#define TIM_DMABase_PSC   ((uint16_t)0x000A)

#define TIM_DMABase_ARR   ((uint16_t)0x000B)

#define TIM_DMABase_RCR   ((uint16_t)0x000C)

#define TIM_DMABase_CCR1   ((uint16_t)0x000D)

#define TIM_DMABase_CCR2   ((uint16_t)0x000E)

#define TIM_DMABase_CCR3   ((uint16_t)0x000F)

#define TIM_DMABase_CCR4   ((uint16_t)0x0010)

#define TIM_DMABase_BDTR   ((uint16_t)0x0011)

#define TIM_DMABase_DCR   ((uint16_t)0x0012)

#define TIM_DMABase_OR   ((uint16_t)0x0013)

#define IS_TIM_DMA_BASE

(

BASE

)

Value:

(((BASE) == TIM_DMABase_CR1) || \
                               ((BASE) == TIM_DMABase_CR2) || \
                               ((BASE) == TIM_DMABase_SMCR) || \
                               ((BASE) == TIM_DMABase_DIER) || \
                               ((BASE) == TIM_DMABase_SR) || \
                               ((BASE) == TIM_DMABase_EGR) || \
                               ((BASE) == TIM_DMABase_CCMR1) || \
                               ((BASE) == TIM_DMABase_CCMR2) || \
                               ((BASE) == TIM_DMABase_CCER) || \
                               ((BASE) == TIM_DMABase_CNT) || \
                               ((BASE) == TIM_DMABase_PSC) || \
                               ((BASE) == TIM_DMABase_ARR) || \
                               ((BASE) == TIM_DMABase_RCR) || \
                               ((BASE) == TIM_DMABase_CCR1) || \
                               ((BASE) == TIM_DMABase_CCR2) || \
                               ((BASE) == TIM_DMABase_CCR3) || \
                               ((BASE) == TIM_DMABase_CCR4) || \
                               ((BASE) == TIM_DMABase_BDTR) || \
                               ((BASE) == TIM_DMABase_DCR) || \
                               ((BASE) == TIM_DMABase_OR))