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STM32LIB
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AHB Peripheral Clock enable register (RCC_AHBENR) More...
#include <STM32F030.hpp>
Public Types | |
| using | DMAEN = reg_t< rw_t, 0X40021014, 0, 1 > |
| DMA1 clock enable. More... | |
| using | SRAMEN = reg_t< rw_t, 0X40021014, 2, 1 > |
| SRAM interface clock enable. More... | |
| using | FLITFEN = reg_t< rw_t, 0X40021014, 4, 1 > |
| FLITF clock enable. More... | |
| using | CRCEN = reg_t< rw_t, 0X40021014, 6, 1 > |
| CRC clock enable. More... | |
| using | IOPAEN = reg_t< rw_t, 0X40021014, 17, 1 > |
| I/O port A clock enable. More... | |
| using | IOPBEN = reg_t< rw_t, 0X40021014, 18, 1 > |
| I/O port B clock enable. More... | |
| using | IOPCEN = reg_t< rw_t, 0X40021014, 19, 1 > |
| I/O port C clock enable. More... | |
| using | IOPDEN = reg_t< rw_t, 0X40021014, 20, 1 > |
| I/O port D clock enable. More... | |
| using | IOPFEN = reg_t< rw_t, 0X40021014, 22, 1 > |
| I/O port F clock enable. More... | |
AHB Peripheral Clock enable register (RCC_AHBENR)
| using STM32LIB::reg::RCC::AHBENR::DMAEN = reg_t<rw_t, 0X40021014, 0, 1> |
DMA1 clock enable.
| using STM32LIB::reg::RCC::AHBENR::SRAMEN = reg_t<rw_t, 0X40021014, 2, 1> |
SRAM interface clock enable.
| using STM32LIB::reg::RCC::AHBENR::FLITFEN = reg_t<rw_t, 0X40021014, 4, 1> |
FLITF clock enable.
| using STM32LIB::reg::RCC::AHBENR::CRCEN = reg_t<rw_t, 0X40021014, 6, 1> |
CRC clock enable.
| using STM32LIB::reg::RCC::AHBENR::IOPAEN = reg_t<rw_t, 0X40021014, 17, 1> |
I/O port A clock enable.
| using STM32LIB::reg::RCC::AHBENR::IOPBEN = reg_t<rw_t, 0X40021014, 18, 1> |
I/O port B clock enable.
| using STM32LIB::reg::RCC::AHBENR::IOPCEN = reg_t<rw_t, 0X40021014, 19, 1> |
I/O port C clock enable.
| using STM32LIB::reg::RCC::AHBENR::IOPDEN = reg_t<rw_t, 0X40021014, 20, 1> |
I/O port D clock enable.
| using STM32LIB::reg::RCC::AHBENR::IOPFEN = reg_t<rw_t, 0X40021014, 22, 1> |
I/O port F clock enable.
1.8.9.1