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STM32LIB
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Macros | |
| #define | SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK |
| #define | SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK |
| #define | SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK |
| #define | IS_SYSCFG_LOCK_CONFIG(CONFIG) |
| #define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK |
Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices
| #define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK |
Connects the SRAM_PARITY error signal to the Break Input of TIM1
| #define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK |
Connects Lockup output of CortexM0 to the break input of TIM1
| #define IS_SYSCFG_LOCK_CONFIG | ( | CONFIG | ) |
1.8.9.1