SYSCFG_DMA_Remap_Config

Macros
#define	SYSCFG_DMARemap_TIM3
#define	SYSCFG_DMARemap_TIM2
#define	SYSCFG_DMARemap_TIM1
#define	SYSCFG_DMARemap_I2C1
#define	SYSCFG_DMARemap_USART3
#define	SYSCFG_DMARemap_USART2
#define	SYSCFG_DMARemap_SPI2
#define	SYSCFG_DMARemap_TIM17_2
#define	SYSCFG_DMARemap_TIM16_2
#define	SYSCFG_DMARemap_TIM17   SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
#define	SYSCFG_DMARemap_TIM16   SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
#define	SYSCFG_DMARemap_USART1Rx   SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
#define	SYSCFG_DMARemap_USART1Tx   SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
#define	SYSCFG_DMARemap_ADC1   SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
#define	IS_SYSCFG_DMA_REMAP(REMAP)

Detailed Description

Macro Definition Documentation

#define SYSCFG_DMARemap_TIM3

Value:

SYSCFG_CFGR1_TIM3_DMA_RMP      /* Remap TIM3 DMA requests from channel4 to channel6, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_TIM2

Value:

SYSCFG_CFGR1_TIM2_DMA_RMP      /* Remap TIM2 DMA requests from channel3/4 to channel7, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_TIM1

Value:

SYSCFG_CFGR1_TIM1_DMA_RMP      /* Remap TIM1 DMA requests from channel2/3/4 to channel6, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_I2C1

Value:

SYSCFG_CFGR1_I2C1_DMA_RMP      /* Remap I2C1 DMA requests from channel3/2 to channel7/6, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_USART3

Value:

SYSCFG_CFGR1_USART3_DMA_RMP    /* Remap USART3 DMA requests from channel6/7 to channel3/2, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_USART2

Value:

SYSCFG_CFGR1_USART2_DMA_RMP    /* Remap USART2 DMA requests from channel4/5 to channel6/7, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_SPI2

Value:

SYSCFG_CFGR1_SPI2_DMA_RMP      /* Remap SPI2 DMA requests from channel4/5 to channel6/7, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_TIM17_2

Value:

SYSCFG_CFGR1_TIM17_DMA_RMP2    /* Remap TIM17 DMA requests from channel1/2 to channel7, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_TIM16_2

Value:

SYSCFG_CFGR1_TIM16_DMA_RMP2    /* Remap TIM16 DMA requests from channel3/4 to channel6, 
                                                                      available only for STM32F072 devices */

#define SYSCFG_DMARemap_TIM17   SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */

#define SYSCFG_DMARemap_TIM16   SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */

#define SYSCFG_DMARemap_USART1Rx   SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */

#define SYSCFG_DMARemap_USART1Tx   SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */

#define SYSCFG_DMARemap_ADC1   SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */

#define IS_SYSCFG_DMA_REMAP

(

REMAP

)

Value:

(((REMAP) == SYSCFG_DMARemap_TIM17) || \
                                    ((REMAP) == SYSCFG_DMARemap_TIM16) || \
                                    ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
                                    ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
                                    ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
                                    ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
                                    ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
                                    ((REMAP) == SYSCFG_DMARemap_ADC1))